Method of forming an inverted t shaped channel structure for an inverted t channel field effect transistor device

ABSTRACT

A method of forming an inverted T shaped channel structure having a vertical channel portion and a horizontal channel portion for an Inverted T channel Field Effect Transistor ITFET device comprises providing a semiconductor substrate, providing a first layer of a first semiconductor material over the semiconductor substrate and providing a second layer of a second semiconductor material over the first layer. The first and the second semiconductor materials are selected such that the first semiconductor material has a rate of removal which is less than a rate of removal of the second semiconductor material. The method further comprises removing a portion of the first layer and a portion of the second layer selectively according to the different rates of removal so as to provide a lateral layer and the vertical channel portion of the inverted T shaped channel structure and removing a portion of the lateral layer so as to provide the horizontal channel portion of the inverted T shaped channel structure.

FIELD OF THE DISCLOSURE

This disclosure relates to method of forming an inverted T shapedchannel structure for an Inverted T channel Field Effect Transistor(ITFET) device, a method of forming an ITFET device and an ITFET device.

BACKGROUND

New transistor device architectures such as double gate transistordevices have been developed to provide improved short channel controlwhich results in improved current characteristics. A FinFET device is anexample of such a double gate device. A simplified cross-section of partof a FinFET device is shown in FIG. 1. A FinFET device is a non-planardevice which includes a conducting channel that is formed on the twoopposite faces of or is wrapped around a thin silicon ‘fin’ 14 formed ona substrate 12 which forms the body of the device. A gate 18 overliesthe fin 14 and a gate dielectric 16. The dimensions of the fin and thenumber of fins in the device determine the effective channel width ofthe device. The FinFET has some limitations due to the space between thefins being electrically inactive.

An ITFET device has been developed which is a FinFET-type device withlateral extensions at the bottom of the fin so as to provide active thinbody devices in the unused regions between the fins which increases thecurrent drive compared to a FinFET device. A simplified cross-section ofpart of an ITFET device is shown in FIG. 2. The fin 24 and lateralextensions 25 form an inverted T shaped channel structure providinghorizontal and vertical channels which are controlled by multiplecontiguous gate segments: gate 28 overlies the fin 24 and a gatedielectric 26. Thus, an ITFET device is a multi gate device combiningvertical and planar thin body structures within a single device. Moredetails of the ITFET device can be found in US patent application no.2007/050317 and an article entitled ‘Inverted T channel FET(ITFET)—Fabrication and Characteristics of Vertical-Horizontal, ThinBody, Multi-Gate, Multi-Orientation Devices, ITFET SRAM Bit-celloperation. A Novel Technology for 45 nm and Beyond CMOS’, by L. Mathewet al, Electron Devices Meeting, 2005. IEDM Technical Digest. IEEEInternational 5-7 Dec. 2005, pages 713-716.

In order not to compromise device performance, the inverted T shapedchannel structure needs to be patterned reliably and repeatedly which isa challenge particularly since the structure has eight corners.Currently, as discussed in the above two documents, the lateralextensions of the inverted T shaped channel structure of the ITFETdevice is manufactured by a timed etch. However, generally, a timed etchprocess (i.e. a main etch process that is performed for a predeterminedtime) does not offer much control and uniformity in a manufacturingenvironment. In other words, with the current process, the thickness ofthe horizontal channel provided by the lateral extensions is hard tocontrol reliably and uniformly.

Thus, there is therefore a need for an improved method of forming anITFET device.

SUMMARY

The present invention provides a method of forming an inverted T shapedchannel structure for an ITFET device, a method of forming an ITFETdevice and an ITFET device as described in the accompanying claims.

BRIEF DESCRIPTION OF THE DRAWINGS

A method of forming an inverted T shaped channel structure for anInverted T channel Field Effect Transistor (ITFET) device, a method offorming an ITFET device and an ITFET device in accordance with thepresent disclosure will now be described, by way of example only, withreference to the accompanying drawings in which:

FIG. 1 is a schematic cross-section diagram of a portion of a knownFinFET device;

FIG. 2 is a schematic cross-section diagram of a portion of a knownITFET device;

FIGS. 3-6 are schematic cross-section diagrams of a portion of an ITFETdevice during different stages of fabrication in accordance with anembodiment of the disclosure;

FIG. 7 is a top view of part of the ITFET device of FIG. 6; and

FIG. 8 is a schematic cross-section diagram of a portion of a partlyfabricated ITFET device showing rounding of active corners of theinverted T shaped channel structure in accordance with an embodiment ofthe disclosure.

DETAILED DESCRIPTION OF THE DRAWINGS

In the description that follows and in FIGS. 3-8, certain regions areidentified as being of a particular material, conductivity and/or type.However, this is merely for convenience of explanation and not intendedto be limiting. Those of skill in the art will understand based on thedescription given herein that various semiconductor materials can beused and that the doping of various regions of the device may be alteredin order to obtain different device functions.

A method of forming an inverted T shaped channel structure for anInverted T channel Field Effect Transistor ITFET device in accordancewith an embodiment of the present disclosure will now be described withreference to FIGS. 3-8. Only part of the ITFET device is shown forsimplicity.

In FIG. 3, a first layer 304 of a first semiconductor material is formedover a semiconductor substrate 302. In an embodiment, semiconductorsubstrate 302 is a silicon oxide substrate (e.g. a SOI substrate) or asubstrate with a silicon oxide layer, or other electrical insulator, atthe top. The semiconductor substrate 302 may be formed from othermaterials. A second layer 306 of a second semiconductor material isformed over the first layer 304 and a mask 308, such as a hard mask orphotoresist, is formed over the second layer 306. In an embodiment, mask308 is a layer of silicon nitride but could be another material orcombination of materials that is effective as an etch mask to the firstand second semiconductor materials. Typically, the first layer 304 has athickness in the range of 10-150 nm and the second layer 306 has athickness in the range of 20-180 nm.

The silicon nitride layer 308 is patterned and etched to from a nitridecap 310 (see FIG. 4). A portion of the first 304 layer is then removedto provide a lateral layer 312 and a portion of the second layer 306 isthen removed so as to form the vertical channel portion or active regionor fin 314 of an inverted T shaped channel structure.

The first and the second semiconductor materials are selected such thatthe first semiconductor material has a rate of removal or etch ratewhich is less than the rate of removal or etch rate of the secondsemiconductor material during the same removal or etch conditions sothat portions of the first layer and second layer are removedselectively according to the different rates of removal. The firstsemiconductor material and second semiconductor material may be selectedfrom the following semiconductor materials: intrinsic semiconductormaterial, intrinsic semiconductor alloy, doped semiconductor material,doped semiconductor alloy and thus includes the following examplesemiconductor materials: silicon; silicon germanium alloy; siliconcarbon alloy; silicon, germanium and carbon alloy; doped silicon; dopedsilicon germanium alloy; doped silicon carbon alloy; and doped silicon,germanium and carbon alloy. The doped semiconductor materials may bedoped in situ or the dopants may be introduced for example byimplantation. In an embodiment, the first and second semiconductormaterials are monocrystalline but may instead be polycrystalline oramorphous.

Thus, by selecting the appropriate semiconductor materials for the first304 and second 306 layers according to their different etch rates duringthe etch process, the lateral layer 312 and the vertical channel portion314 of the inverted T shaped channel structure can be formed. Dryetching or wet etching processes may be used to remove the portions ofthe first 304 and second 306 layers.

In one example, the first semiconductor material is silicon germaniumalloy and the second semiconductor material is silicon. The first SiGelayer 304 is grown epitaxially on the substrate 302 and the second Silayer 306 is grown epitaxially on the first SiGe layer 304. One of thefollowing etchants is then used to etch selectively the first 304 andsecond 306 layers to form the lateral layer 312 and the vertical channelportion 314: a combination of carbon tetrafluoride CF₄, oxygen 0₂, ArgonAr and nitrogen N₂. For example, a reactive ion plasma etch may be usedto selectively etch the first SiGe layer 304 and the second Si layer 306with gases: CF₄, O₂, Ar. The following combination of gases may also beused in an etch process: CF₄/CH₂F₂/N₂/O₂/Ar.

The etch rate of the SiGe of the first layer 304 depends on theconcentration of germanium in the SiGe alloy: the higher theconcentration of germanium, the greater the etch rate. When theconcentration of silicon to germanium in the first layer 304 is in theratio 8:2, the Si etch rate is 250 nm/min and a selectivity of over 100can be readily achieved. This means that the second Si layer 306 isetched at a greater rate than the first SiGe layer 304.

In another example, the first semiconductor material is silicon Si andthe second semiconductor material is silicon germanium SiGe alloy. Thefirst Si layer 304 is grown epitaxially on the substrate 302 and thesecond SiGe layer 306 is grown epitaxially on the first Si layer 304.One of the following etchants is then used to etch selectively the first304 and second 306 layers to form the lateral layer 312 and the verticalchannel portion 314: nitric acid HNO₃, and a combination of hydrogenperoxide H₂O₂, hydrogen fluoride HF and acetic acid CH₃COOH. Forexample, a wet etch using a solution containing HNO₃, H₂O₂, and HF maybe used to selectively etch the first Si layer 304 and second SiGe layer306. A dry etch, for example, using the plasma etch processes describedabove may also be used.

The etch rate of the SiGe of the second layer 306 depends on theconcentration of germanium in the SiGe alloy: the higher theconcentration of germanium, the greater the etch rate. When theconcentration of silicon to germanium in the second layer 306 is in theratio 9:1, the selectivity to the SiGe alloy compared to Si is about 25.When the concentration of silicon to germanium in the second layer 306is in the ratio 71:39, the selectivity to the SiGe alloy compared to Siis about 60. For both example concentrations of Ge, the second layer 306is etched at a greater rate than the first layer 304 (but at a greaterrate for the second example).

In principle, the selectivity could be maximised and hence the etch rateof the SiGe alloy increased by having the Ge concentration in the SiGealloy greater than 50%. However, higher Ge concentrations (for exampleover 60%) may induce high mechanical stresses which could render thedevice inoperable because of the high level of defects or delaminationeffects. It will be appreciated that the range of Ge concentration isslightly different for the case when the first layer 304 is Si and thesecond layer 306 is SiGe compared to the case when the first layer 304is SiGe and the second layer 306 is Si and depends on the etchchemistry.

In the examples described above, the first 304 and second 306 layers aregrown epitaxially on the substrate 302, which may be a SOI waferprovided by a wafer vendor, such as SOITEC. Alternatively, the wafervendor may provide an SOI wafer (substrate 302) with crystalline Sifirst layer 304 on the oxide layer 302 or an SOI wafer with crystallineSiGe first layer 304 on the oxide layer 302. The second layer 306 wouldthen be grown epitaxially on the pre-existing first layer 304 providedby the wafer vendor.

In another example, the first semiconductor material comprises at leasttwo semiconductor materials and the second semiconductor materialcomprise the same at least two semiconductor materials but in differentconcentrations to that of the first semiconductor material. For example,the first semiconductor material is silicon germanium alloy with 10% Geconcentration and the second semiconductor material is silicon germaniumalloy with 40% Ge concentration and the solution HNO₃ is used in theetch process. In another example, the first semiconductor material issilicon germanium alloy with 30% Ge concentration and the secondsemiconductor material is silicon germanium alloy with 10% Geconcentration and the solution CF₄/0₂/N₂ is used in the etch process.

Other examples include: the first semiconductor material is Si and thesecond semiconductor material is any one of SiC, Si/Ge/C, doped SiC,doped Si/Ge/C; the first semiconductor material is SiGe and the secondsemiconductor material is any one of SiC, Si/Ge/C, doped SiC, dopedSi/Ge/C; the first semiconductor material is SiC and the secondsemiconductor material is any one of SiC (with different concentrationsof C to the first semiconductor material), Si/Ge/C, doped SiC, dopedSi/Ge/C; the first semiconductor material is Si/Ge/C and the secondsemiconductor material is any one of SiC, Si/Ge/C (with differentconcentrations of C and Ge to the first semiconductor material), dopedSiC, doped Si/Ge/C; or any other suitable combinations of first andsecond semiconductor materials. The appropriate etchants (wet or dry)are selected in order to achieve selective etching of the first andsecond semiconductor materials.

More information concerning selective etch processes can be found in thefollowing articles: “Impact of Tunnel Etching Process on ElectricalPerformance of SON devices”, by V. Caulet et al, Japanese Journal ofApplied Physics, vol. 44, no. 7B, p. 5795-98, 2005; and“Silicon-on-Nothing (SON)—an innovative process for advanced CMOS” byJurczak, M.; Skotnicki, T.; Paoli, M.; Tormen, B.; Martins, J.;Regolini, J. L.; Dutartre, D.; Ribot, P.; Lenoble, D.; Pantel, R.;Monfray, S published in IEEE Transactions on Electron Devices, vol. 47,Page(s): 2179-2187, 2000.

The subsequent process steps follow the conventional method of formingan ITFET.

Referring now to FIG. 5, a liner 318 is then formed over lateral layer312, nitride cap 310 and vertical channel portion 314. Liner 318 may besilicon oxide that is thermally grown or deposited. Sidewall spacer 320is then formed on the sidewalls of vertical channel portion 314. In apreferred embodiment, sidewall spacer 320 is formed of silicon nitridebut could be formed of another material that can function as an etchmask.

A portion of the lateral layer 312 is then removed using sidewall spacer320 as a mask and an etching process so as to form horizontal channelportion or horizontal active region 322 of the ITFET device, as shown inFIG. 6. Thus, the width of the horizontal channel portion 322 isdetermined by the width of the sidewall spacer 320. Sidewall spacer 320,liner 318 and nitride cap 310 are then removed. A gate dielectric 324 isformed over the horizontal channel portion 322 and vertical channelportion 314 and then a gate 326 is formed over the dielectric gate 324.In an embodiment, the gate dielectric 324 is formed by a hightemperature growth of silicon oxide. Other dielectric materials, such asmetal oxides Hf0₂ or Zr0₂, or any suitable high-k dielectric material,may alternatively be used. The gate 326 may be formed of a conductivematerial such as polysilicon or polysilicon on metal. The source anddrain regions 328 are formed in conventional fashion as for a FinFETdevice.

FIG. 7 is a top perspective view of part of the ITFET device of FIG. 6(but not showing the gate dielectric 324 separately) and showssource/drain regions 328 on either side of the gate 326 and formed overthe semiconductor substrate 302. In the example shown in FIG. 7, thesource/drain regions 328 are formed over part of the lateral layer 312.

In an ITFET device comprising a plurality of ‘fins’ or inverted T shapedchannel structures, each of the plurality of ‘fins’ are formed in thesame ways as described above.

The inverted T shaped channel structure of an ITFET device has eightcorners. When the corners are pointed or not rounded, prematureinversion can take place in the convex corner regions with the resultthat different parts of the ITFET device are switched on at differentgate voltages. Acute concave corners are likely to suffer from deferredonset of inversion. In order to avoid premature or deferred inversion atthe corners and to provide the same inversion properties along thelength of the ITFET device, it is desirable to have rounded activecorners on the vertical channel portion 314 and the horizontal channelportion 322 of the inverted T shaped channel structure.

In an embodiment of the disclosure, one of the first and secondsemiconductor materials is selected to be an intrinsic semiconductoralloy comprising at least a first semiconductor and a secondsemiconductor, with the concentration of the second semiconductorincreasing as a distance from the junction between the first 304 andsecond 306 layers increases to a predetermined distance after which theconcentration of the second semiconductor is constant. By varying theconcentration of the second semiconductor as a function of distance fromthe junction between the first 304 and second 306 layers, desired andrelatively precise corner rounding can be engineered.

FIG. 8 shows the corner rounding at 342 in an example where the firstlayer 304 is Si and the second layer 306 is SiGe. The graph in FIG. 8shows how the concentration of Ge in the second layer 306 (which formsthe vertical channel portion 314) varies with distance z from thejunction 340 between the first 304 and second 306 layers. The Geconcentration in the second semiconductor material is varied when thesecond SiGe layer 306 is formed by epitaxial growth in accordance withwell known processes.

More precise corner rounding can be achieved due to the fact that therate of removal of the second SiGe layer 306 is determined by the localconcentration of Ge and the corner rounding is achieved by theincreasing Ge concentration as the distance from the Si/SiGe junctionincreases until a predetermined distance is reached at 344 where the Geconcentration is kept constant for the upper part of the verticalchannel portion 314. In this way a more precise corner rounding can beengineered. The curvature of radius of the rounded convex and concavecorners can be anywhere between 2-15 nm. The distance from the Si/SiGejunction to 344 may be in the range 3-30 nm.

In an embodiment where the first semiconductor layer 304 is a SiGe layerand the second semiconductor layer 306 is a Si layer, the concentrationof Ge in the first SiGe semiconductor layer 304 decreases from thebottom of the SiGe layer 304 towards the top of the SiGe layer 304adjacent the junction with the second Si layer 306.

Typically, the percentage of Ge used in the SiGe material is 5-50%.

Since the selectivity of the selective removal of portions of the first304 and second 306 layers can be controlled by selecting the appropriatefirst and second semiconductor materials for the first 304 and second306 layers, the thickness 316 of the lateral layer 312 can be controlledmore precisely than a timed etch process. Since the horizontal channelportion of the ITFET device is formed from the lateral layer 312, thethickness of the horizontal channel portion or horizontal active area ofthe ITFET device can therefore be controlled more precisely (e.g. withina few nanometres) than a timed etch process. Typically, the horizontalchannel portion of the ITFET has a thickness in the range of 2-50 nm.

By having a graded concentration of a semiconductor alloy which formsone of the first and second layers which is graded away from thejunction between the first and second layers, well controlled roundingof the active corners of the inverted T shaped channel structure can beprovided. As discussed above, corner rounding avoids premature ordeferred inversion in the corner regions. Since well controlled roundingof the corners can be obtained by the above described graded method inaccordance with an embodiment of the invention, the threshold voltage Vtcan be selected according to the degree of rounding and is kept the samein all parts of the ITFET device so that proper operation of the ITFETdevice can be achieved.

Thus, in summary, the method in accordance with the present disclosureprovides a highly robust and manufacturable method of producing theinverted T channel shaped structure of an ITFET device with the benefitof mobility enhancement. In an embodiment which provides for cornerrounding, the method in accordance with the embodiment providesconvenient corner rounding and convenient adjusting of the thresholdvoltage.

In the foregoing specification, the invention has been described withreference to specific examples of embodiments of the invention. It will,however, be evident that various modifications and changes may be madetherein without departing from the broader scope of the invention as setforth in the appended claims.

1. A method of forming an inverted T shaped channel structure having avertical channel portion and a horizontal channel portion at the bottomof the vertical channel portion for an Inverted T channel Field EffectTransistor ITFET device comprising: providing a semiconductor substrate;providing a first layer of a first semiconductor material over thesemiconductor substrate; providing a second layer of a secondsemiconductor material over the first layer; etching the first layer andthe second layer, the first and the second semiconductor material beingselected such that for same etch conditions the first semiconductormaterial has an etch rate which is less than an etch rate of the secondsemiconductor material and an etch rate across the second layerincreases as a distance from a junction between the first and secondlayers increases to a predetermined distance after which the etch rateof the second semiconductor layer is constant, wherein during theetching, portions of the first layer and the second layer are removedselectively according to the different etch rates so as to provide alateral layer over the semiconductor substrate and the vertical channelportion of the inverted T shaped channel structure with rounded cornersat a junction between the vertical channel portion and the laterallayer; and removing a portion of the lateral layer so as to provide thehorizontal channel portion of the inverted T shaped channel structure.2. A method according to claim 1, wherein the first semiconductormaterial and second semiconductor material are selected from thefollowing semiconductor materials: intrinsic semiconductor material,intrinsic semiconductor alloy, doped semiconductor material, dopedsemiconductor alloy.
 3. A method according to claim 1, wherein the firstsemiconductor material and second semiconductor material are selectedfrom the following semiconductor materials: silicon; silicon andgermanium alloy; silicon and carbon alloy; silicon, germanium and carbonalloy; doped silicon; doped silicon and germanium alloy; doped siliconand carbon alloy; and doped silicon, germanium and carbon alloy.
 4. Amethod according to claim 1, wherein the first semiconductor materialcomprises at least two semiconductor materials and the secondsemiconductor material comprise the same at least two semiconductormaterials but in different concentrations to that of the firstsemiconductor material.
 5. A method according to claim 1, whereinetching selectively comprises etching the first and second layers usingan etchant selected from the following: HNO3; a combination of H2O2, HFand CH3COOH; a combination of H2O2, HF and HNO3; a combination of CF4,02 and Ar; a combination of CF4, 02 and N2; and a combination of CF4,CH2F2, N2, O2, and Ar.
 6. A method according to claim 1, furthercomprising: forming a sidewall spacer on a first side and a second sideof the vertical channel portion, wherein the removing a portion of thelateral layer comprises removing a portion of the lateral layer which isnot covered by the sidewall spacer; and removing the sidewall spacer. 7.A method according to claim 1, wherein one of the first and secondsemiconductor materials is selected to be an intrinsic semiconductoralloy comprising at least a first semiconductor and a secondsemiconductor, with a concentration of the second semiconductorincreasing as a distance from a junction between the first and secondlayers increases to a predetermined distance after which theconcentration of the second semiconductor is constant.
 8. A methodaccording to claim 7, wherein the other one of the first and secondsemiconductor materials is selected to be one of the first semiconductorand an intrinsic semiconductor alloy comprising at least the firstsemiconductor and the second semiconductor, with a concentration of thesecond semiconductor in the other one of the first and secondsemiconductor materials being different to the concentration of thesecond semiconductor in the one of the first and second semiconductormaterials.
 9. A method according to claim 7, wherein the one of thefirst and second semiconductor materials is SiGe, the firstsemiconductor being Si and the second semiconductor being Ge.
 10. Amethod of forming an Inverted T channel Field Effect Transistor ITFETdevice comprising: forming an inverted T shaped channel structure havinga vertical channel portion and a horizontal channel portion according toclaim 7; forming a gate dielectric over at least a first part of thehorizontal channel portion and at least a first part of the verticalchannel portion; forming a gate over the gate dielectric; and forming asource region and drain region over the semiconductor substrate eitherside of the gate.
 11. (canceled)
 12. A method according to claim 2,wherein the first semiconductor material comprises at least twosemiconductor materials and the second semiconductor material comprisethe same at least two semiconductor materials but in differentconcentrations to that of the first semiconductor material.
 13. A methodaccording to claim 2, wherein etching selectively comprises etching thefirst and second layers using an etchant selected from the following:HNO3; a combination of H2O2, HF and CH3COOH; a combination of H2O2, HFand HNO3; a combination of CF4, 02 and Ar; a combination of CF4, 02 andN2; and a combination of CF4, CH2F2, N2, O2, and Ar.
 14. A methodaccording to claim 3, wherein etching selectively comprises etching thefirst and second layers using an etchant selected from the following:HNO3; a combination of H2O2, HF and CH3COOH; a combination of H2O2, HFand HNO3; a combination of CF4, 02 and Ar; a combination of CF4, 02 andN2; and a combination of CF4, CH2F2, N2, O2, and Ar.
 15. A methodaccording to claim 4, wherein etching selectively comprises etching thefirst and second layers using an etchant selected from the following:HNO3; a combination of H2O2, HF and CH3COOH; a combination of H2O2, HFand HNO3; a combination of CF4, 02 and Ar; a combination of CF4, 02 andN2; and a combination of CF4, CH2F2, N2, O2, and Ar.
 16. A methodaccording to claim 2, further comprising: forming a sidewall spacer on afirst side and a second side of the vertical channel portion, whereinthe removing a portion of the lateral layer comprises removing a portionof the lateral layer which is not covered by the sidewall spacer; andremoving the sidewall spacer.
 17. A method according to claim 4, furthercomprising: forming a sidewall spacer on a first side and a second sideof the vertical channel portion, wherein the removing a portion of thelateral layer comprises removing a portion of the lateral layer which isnot covered by the sidewall spacer; and removing the sidewall spacer.18. A method according to claim 2, wherein one of the first and secondsemiconductor materials is selected to be an intrinsic semiconductoralloy comprising at least a first semiconductor and a secondsemiconductor, with a concentration of the second semiconductorincreasing as a distance from a junction between the first and secondlayers increases to a predetermined distance after which theconcentration of the second semiconductor is constant.
 19. A methodaccording to claim 4, wherein one of the first and second semiconductormaterials is selected to be an intrinsic semiconductor alloy comprisingat least a first semiconductor and a second semiconductor, with aconcentration of the second semiconductor increasing as a distance froma junction between the first and second layers increases to apredetermined distance after which the concentration of the secondsemiconductor is constant.
 20. A method according to claim 6, whereinone of the first and second semiconductor materials is selected to be anintrinsic semiconductor alloy comprising at least a first semiconductorand a second semiconductor, with a concentration of the secondsemiconductor increasing as a distance from a junction between the firstand second layers increases to a predetermined distance after which theconcentration of the second semiconductor is constant.
 21. A methodaccording to claim 8, wherein the one of the first and secondsemiconductor materials is SiGe, the first semiconductor being Si andthe second semiconductor being Ge.